Tianen Chen

Biography

I received my BA in Physics from Carleton College and a BS in Electrical Engineering from Columbia University in the City of New York. Currently, I am a PhD student in Electrical and Computer Engineering at UW-Madison in the WISEST lab.

Education

• University of Wisconsin-Madison, Madison, WI
  • PhD in Electrical and Computer Engineering
• Columbia University, New York, NY
  • BS in Electrical Engineering
• Carleton College, Northfield, MN
  • BA in Physics

Research Interests

• Machine learning
• Approximate computing
• Low power embedded systems
• Internet of things

Awards and Honors

• IWLS Programming Contest First Place, 2021
  • Area-efficient CIFAR-10 Classification based on XGBoost
• Intel Distinguished Invention Award, 2020
• NSF GRFP Fellow, 2020
  • Deterministic Input Pruning for Hardware Minimization of Neural Networks
• Qualcomm Innovation Fellowship Finalist, 2020
  • Ultra Low-Power Machine Learning at The Edge
• Foxconn “Smart Cities-Smart Futures” Competition Final Winner for “ReadyVue” proposal, 2020
• Student Research Conference Grant Award, 2019 & 2020
• Foxconn “Smart Cities-Smart Futures” Competition Final Winner for “Nightshift” proposal, 2019
• Richard Newton Young Student Fellowship, 2019
• Wisconsin Distinguished Fellowship Award, 2018
• Cum Laude honors at Columbia University, 2018

Published Papers:

1. SynthNet: A High Throughput yet Energy-efficient Combinational Logic Neural Network
   Tianen Chen, Taylor Kemp, and Younghyun Kim
   ASPDAC, (Asia and South Pacific Design Automation Conference), 2022
   1. Designed and implemented a low-power combinational logic neural network.
   2. Exploited the error-resiliency of neural networks to perform iterative logic minimization for scalable networks.
   3. Synthesized combinational circuits and classified datasets using purely combinational hardware.
   4. Reduced power consumption by 90% while maintaining 80%+ accuracy on CIFAR-10 dataset.
2. Approximate Hardware Techniques for Energy-Quality Scaling Across the System
   Younghyun Kim, Joshua San Miguel, Setareh Behroozi, Tianen Chen, Kyuin Lee, Yongwoo Lee, Jingjie Li, and Di Wu
   ICEIC, (International Conference on Electronics, Information, and Communication), 2020
   1. Survey of hardware approximation techniques for dynamic energy-quality scaling.
3. SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization
   Di Wu, Tianen Chen, Chienfu Chen, Oghenefego Ahia, Joshua San Miguel, Mikko Lipasti, and Younghyun Kim
   ISLPED, (International Symposium on Low-Power Electronics and Design), 2019
   1. Designed an approximate exponential function for energy-efficient computation by leveraging Taylor series.
   2. Implemented the approximation into a adaptive exponential integrate-and-fire neuron model.
   3. Used multiple approximate multiplier libraries in order to find optimal low-power design.

Research Experience:

• Doctoral Research Assistant, WISEST Lab, University of Wisconsin-Madison (September 2018 – present).
• Undergraduate Research Assistant, Sickles lab for Nuclear Physics, University of Illinois, Champaign, Illinois (Summer 2016).
• Undergraduate Research Assistant, Cyclotron Institute for Nuclear Physics, Ko lab, College Station, Texas (Summer 2015).

Demos:

1. n-hot Weight Quantization and Approximate Multiplication for Low-Power Machine Learning
   Tianen Chen, John Rupel, Ammar Mahmood, Luciano Ricotta, Younghyun Kim, Joshua San Miguel
   ISLPED, (International Symposium on Low-Power Electronics and Design), 2020
   1. Approximate a neural network with fixed-point weights and then convert them into partial summations of powers of two that can be generated by bit-shifting operations in order to reduce hardware energy consumption.

Industry Experience:

• SOC Design Team Intern, Qualcomm, San Diego, California (Summer 2022)
  • Worked with the Platform Architecture team at Qualcomm to reduce data interconnect power by employing low-power data encoding techniques

  • Engineered content-aware power optimization techniques to optimize performance for on-chip and off-chip networks

• Datapath Intern, Intel Technologies, Folsom, California (Summer 2020)
  • Engineered approximate computing design for datapath efficiencies within microprocessor architecture

  • Performed formal verification on multiple approximate hardware designs

  • Received Intel Distinguished Invention Award for contributions to approximate computing patents

• CAD Photolithography Intern, Seagate Technologies, Bloomington, Minnesota (Summer 2017)
  • Extracted, transformed, and loaded data from multiple databases using SQL

  • Performed database maintenance and improve database schema design

• Morgridge Entrepreneurship Bootcamp, UW-Madison, Madison, Wisconsin (Summer 2018)
  • MBA BootCamp designed for learning business skills as engineers

Services

• External reviewer:
  • DAC, 2020
  • DAC, 2019
  • SAC, 2018
  • ISLPED, 2019