BIOGRAPHY
Yongwoo Lee received the B.S. and M.S. degrees in Electronic Engineering from Sogang University, Korea, in 2006 and 2008, respectively. In 2008, He has joined SK Hynix, Korea, where he has been involved in researching in memory circuit design and verification. He is currently pursuing Ph.D. degree in Electrical and Computer Engineering at the University of Wisconsin-Madison under the guidance of Prof. Younghyun Kim.
EDUCATION
- Ph.D. in Electrical and Computer Engineering, University of Wisconsin-Madison, 2016-present
- M.S. in Electronic Engineering, Sogang University, Korea, 2008
- B.S. in Electronic Engineering, Sogang University, Korea, 2006
RESEARCH INTERESTS
- Embedded systems
- Memory systems
- Approximate computing
- Mobile computing and security
PUBLICATION
International Conferences
- AxFTL: Exploiting Error Tolerance for Extending Lifetime of NAND Flash Storage
Yongwoo Lee, Jaehyun Park, Junhee Ryu, Younghyun Kim
CASES (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems), 2020
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020 - Approximate Hardware Techniques for Energy-Quality Scaling Across the System
Younghyun Kim, Joshua San Miguel, Setareh Behroozi, Tianen Chen, Kyuin Lee, Yongwoo Lee, Jingjie Li, Di Wu
ICEIC (International Conference on Electronics, Information, and Communication), Barcelona, Spain, 2020 - MicPrint: Acoustic Sensor Fingerprinting for Spoof-Resistant Mobile Device Authentication
Yongwoo Lee, Jingjie Li, Younghyun Kim
MobiQuitous (International Conference on Mobile and Ubiquitous Systems: Computing, Networking and Services), Houston, TX, 2019 - CamPUF: Physically Unclonable Function based on CMOS Image Sensor Fixed Pattern Noise
Younghyun Kim, Yongwoo Lee
DAC (Design Automation Conference), San Francisco, CA, 2018. - Design Considerations of HBM Stacked DRAM and the Memory Architecture Extension
Dong Uk Lee, Kang Seol Lee, Yongwoo Lee, Kyung Whan Kim, Jong Ho Kang, Jae-Jin Lee and Jun Hyun Chun
CICC (Custom Integrated Circuits Conference), San Jose, CA, 2015.
Patents
- Memory Device and System including the same
Chang-Hyun Kim, Min-Chang Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hun-Sam Jung, Hoe-Kwon Jung
US20170221545A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hun-Sam Jung
US20170109277A1, 2017 - Memory System
Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109274A1, 2017 - Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109086A1, 2017
- Memory System
Yongwoo Lee, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Jae-Jin Lee, Hun-Sam Jung
US20170109077A1, 2017
- Memory System
Chang-Hyun Kim, Min-Chang Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hun-Sam Jung
US20170109076A1, 2017
- Memory System
Yongwoo Lee, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Jae-Jin Lee, Hun-Sam Jung
US20170109075A1, 2017
- Memory System
Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yongwoo Lee, Jae-Jin Lee, Hun-Sam Jung
US20170109074A1, 2017
- Memory System
Chang-Hyun Kim, Min-Chang Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109073A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hun-Sam Jung
US20170109072A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109071A1, 2017
- Memory System
Chang-Hyun Kim, Min-Chang Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109070A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109069A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109068A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109067A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109065A1, 2017
- Memory System
Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109063A1, 2017
- Memory System
Jae-Jin Lee, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Hoe-Kwon Jung
US20170109061A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hoe-Kwon Jung
US20170109060A1, 2017
- Memory System
Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yongwoo Lee, Jae-Jin Lee, Hun-Sam Jung
US20170109043A1, 2017
- Test Apparatus, Test System and Operating Method of Test Apparatus
Yongwoo Lee
US20160133339A1, 2016
- Pin Removal Mode Signal Generation Circuit and Semiconductor Apparatus including the same
Yongwoo Lee
US9239354B2, 2016
- Majority Determination Circuit, Majority Determination Method, and Semiconductor Device
Yongwoo Lee
US20140359402A1, 2014
AWARDS AND HONORS
- FY20 Fall Travel Grant award, UW-Madison, 2019
- Student Research Grants Competition (SGRC), UW-Madison, 2019
- The Best Demonstration Award in SIGDA University Demonstration, DAC, 2018.
- The 2nd Place in 2017 KOCESA Moon-Jung Chung Scholarship Competition, KOCSEA Technical Symposium, 2017.
- Ph.D. Program Fellowship (Recipient: 0.1% of employees), SK Hynix, 2014.
RESEARCH EXPERIENCE
Research Assistant at WISEST Lab, University of Wisconsin-Madison, Sep. 2017–Present
- Memory system and approximate computing
- AxFTL: Exploiting error tolerance for extending lifetime of NAND flash storage
- Mobile computing and security
- CamPUF: Physically unclonable function based on CMOS image sensor fixed pattern noise
- MicPrint: Acoustic sensor fingerprinting for spoof-resistant mobile device authentication
Research Assistant at Man-Machine Interface Lab, Sogang University, Korea, Sep. 2006–Jul. 2008
- Object detection and tracking
- Robust license plate extraction method for low-quality images
- Hand tracking using the modified KLT features for sign language recognition
INDUSTRY EXPERIENCE
Memory Circuit Design and Verification, SK Hynix, Korea, Aug.2008-Dec.2015
- Managed DRAM Solution (MDS)
- DRAM circuit optimization and evaluation for MDS
- Memory Verification
- Full chip verification using Verilog HDL simulation, DDR3, DDR4, and HBM SDRAM
- DDR4 Verilog product model development and management
- Memory Circuit Design
- Control logic design for NVDIMM, 16 GB NVDIMM based on 20-nm class 4 Gb DDR4 SDRAM
- Control logic design for refresh enhancement and test logic for silicon debugging, 20-nm class 4 Gb DDR4 SDRAM
- Command/Address circuit design and through silicon via (TSV) decoders, 128 GB DDR4 memory module based on 20-nm class 8 Gb DDR4 SDRAM
- Data/Address/Command receiver circuit design, 30/40-nm class 2 Gb DDR3 SDRAM
- Fail Analysis
- Silicon debugging for full-chip logic validation using post-simulation and Verilog HDL simulation, 20-nm class 4 Gb/8 Gb DDR4 SDRAM
- Silicon matching and debugging for data/address/command receiver using post-simulation, 30/40-nm class 2 Gb DDR3 SDRAM
SERVICES
External Reviewer
- TECS (Transactions on Embedded Computing Systems), 2020
- DAC (Design Automation Conference), 2018, 2019, 2020
- ISLPED (International Symposium on Low Power Electronics and Design), 2018, 2019
- ASP-DAC (Asia and South Pacific Design Automation Conference), 2019
- VLSID (International Conference on VLSI Design), 2019
- SAC (Symposium on Applied Computing), 2019